1. Field of the Invention
The present invention relates to semiconductor devices and processing, and in particular, to electroplating and fabrication of layers prior to electroplating.
2. Discussion of the Related Art
Integrated circuits fabricated on semiconductor substrates for very and ultra large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next.
As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers needs to be as small as possible. One way to reduce the size of interconnection lines and vias is to use copper (Cu) as the interconnect material instead of conventionally used materials such as aluminum (Al). Because copper has lower resistivities and significantly higher electromigration resistance as compared to aluminum, copper advantageously enables higher current densities experienced at high levels of integration and increased device speed at higher frequencies. Thus, major integrated circuit manufacturers are transitioning from aluminum-based metallization technology to dual damascene copper technology.
However, the use of copper as the interconnect material presents various problems. For example, there is currently no production-worthy dry etch process for Cu. This necessitates the use of a dual damascene xe2x80x9cinlaidxe2x80x9d approach. In the dual damascene approach, a dielectric or insulating diffusion barrier layer is deposited over a copper layer. The dielectric layer is then patterned, e.g., by conventional masking and etching techniques, to form a two-step connection having a narrower lower portion (or via portion) exposing desired connection areas on the underlying patterned metal layer and a wider upper portion (or trench portion) that will form the next layer of metal lines. Copper is then deposited to fill the via and trench, such as by electroplating. Excess copper is then removed, e.g., by a chemical mechanical polish (CMP) process. The resulting structure is a via (the filled via portion) connecting the desired areas in the underlying metal layer with an overlying copper line (the filled trench portion).
One of the consequences of using copper is that copper atoms can readily diffuse into adjacent ILD or other dielectric layers, which can compromise their integrity as insulators or cause voids in the conductors because of out-diffusion of the copper. As a result, a diffusion barrier layer is typically formed over the trenches and vias prior to forming the copper layer. Materials for the barrier layer include Tantalum (Ta), Tungsten Nitride (WN), Titanium Nitride (TiN), Tantalum Nitride (TaN), Silicon Nitride (SiN), and Tungsten (W). The barrier layer may be conformally deposited using a conventional chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process or other known deposition process.
This technique relies on electroplating to fill small features (of order 100 nm in width) with copper. In order for this to work, a xe2x80x9cseed layerxe2x80x9d must be applied to the wafer to provide enough electrical conductance across the wafer, so that a sufficiently uniform layer can be electroplated. In order to electroplate copper, the underlying surface has to be able to conduct current across its surface since electroplating is an electrochemical process. The diffusion barrier typically has high sheet resistivity. Because current must flow through this layer to reach the center portions of the wafer, the voltage drop between the wafer center and its edge may be excessive. Thus, a highly conductive seed layer, typically copper, is deposited over the diffusion barrier. Deposition can be performed by any suitable process, such as PVD.
A key property of the seed layer is that it should have a low sheet resistance per square. Processes in the field at present require less than 1 ohm per square seed resistance, although with improvements in electroplating technology, films as resistive as 5 ohms per square may eventually be suitable seeds. The approximate thickness of films needed to achieve this sheet resistance is shown for various metals in Table 1 below.
These calculations are based on the bulk conductivity of the metals listed. In practice, a larger thickness is needed. The thin film material used does not achieve bulk conductivity, and electron scattering effects also decrease the effective conductivity of such thin films. One problem with depositing a thin copper seed layer is that they do not generally coat the barrier layer in a uniform manner. Rather, voids or non-continuous seed layer regions on the sidewalls are often present, thereby resulting in the inability to properly apply a subsequent electrochemically deposited copper layer. When a discontinuity is present in the seed layer, the portion of the seed layer that is not electrically connected to the bias power supply does not receive deposition during the electroplating process. This is particularly prevalent with high aspect ratio, sub-micron features, where the bottom surface of these features are especially difficult to fill using PVD.
Further, thin seed layers tend to include spikes that impact the uniformity of the subsequent electrolytically deposited metal layer. Such spikes result in high potential regions at which the copper deposits at a higher rate than at other, more level regions. During the electroplating, the voltage and current near the perimeter of the wafer tends to be substantially higher than the voltage and current near the central portions of the wafer. Consequently, copper plates onto the surface of the wafer much more rapidly towards the edges of the wafer, resulting in thicker copper layers towards the perimeter of the wafer. A thicker seed layer can offset this characteristic. Moreover, as shown by Broadbent et al., J. Vac. Sci. Technol., B 17(6), p. 2584 (1999), which is incorporated by reference, the features etched into the dielectric that are coated with the seed layer increase the effective sheet resistance, so that a still thicker seed layer is called for.
However, there is a limit to the combined barrier and seed layer thickness that can be deposited inside features while still allowing for filling of the feature by electroplating. The limit arises because there is a maximum aspect ratio of a feature that can be successfully filled by electroplating. Until now, PVD has been used to deposit the seed layers. As shown in FIG. 1A, PVD forms a seed layer 10 having a much thicker layer on the planar surface (xe2x80x9cfieldxe2x80x9d) of the wafer than within the small features such as vias 20 and trenches. The thicker material in the field allows current to be conducted across the wafer, while there is sufficient copper in the features to allow electroplating in the features. With lower aspect ratio features, e.g.,  less than 3:1, the opening of feature stays open long enough to allow a void-free fill with the electroplating.
But successive reduction in feature sizes has meant that there is increasing difficulty in this process. When the seed layer is formed on the sidewalls as well as the bottom of the feature, the electroplating process deposits the metal on both surfaces within the feature. FIG. 1A shows the opening of the feature being xe2x80x9cclosed offxe2x80x9d with seed layer deposition by PVD. With higher aspect ratio features, the electroplated metal growth on the wall tends to close off the feature at the aperture opening before the feature has been completely filled, resulting in a void 30 forming within the feature, as shown in FIG. 1B. The void changes the material and operating characteristics of the interconnect feature and may cause improper operation and premature breakdown of the device. Thus, with current processes, relatively thin copper seed layers are necessary to fill high aspect ratio features void-free.
The combined barrier and seed thickness that can be tolerated is projected to decrease from present day levels of 15-20 nm down to about 10 nm for future processes. As can be seen from Table 1, only copper (of the materials in the table) can be deposited at this thickness and still provide adequate conductivity in the field, assuming that a completely conformal layer is deposited. Also, the technology advances needed to coat such resistive films (even copper films) increase the cost of the equipment and process.
Thus, it has been difficult to electroplate copper films on semiconductor wafers with both good uniformity of thickness and good gap fill properties.
In accordance with the present invention, copper bus bars are formed between die on a semiconductor wafer. Features, such as trenches and vias, are etched in overlying dielectric layers. Contacts are etched along the bus bars to allow electrical conductance between the bus bars and the features on the die. A platable barrier or a thin copper seed layer allows current flow between the copper bus bars and the trenches and vias. The trenches and vias are then filled using conventional electroplating. The bus bars provide substantial current flow from the wafer edge to wafer center, so that the thin seed or platable barrier is relieved of the need to carry this current. This allows the sheet resistance of the platable barrier or seed layer to be much higher than with previous electrofill methods. Consequently, seed layers can be thinner with a thicker, more reliable barrier layer, and seed layers can be made from materials other than copper.
In one embodiment, the bus bar formation is integrated with the tungsten metallization step generally used at the first metallization level, to provide via contacts to the transistors. A dielectric layer is first deposited over the wafer and die, where the die have active elements formed thereon, such as transistors. The dielectric layer is then patterned and vias are etched to expose selected active elements on each die. Next, the dielectric layer and underlying silicon are etched to create deep intersecting trenches between adjacent die. Upon completion of the processing, the wafer is sawed along the trenches to separate the individual die. In one embodiment, the trenches are 50-100 xcexcm wide and 2-5 xcexcm deep, with a 15 mm pitch.
Thin conformal contact and barrier layers are deposited over the vias and trenches, e.g., 10 nm CVD Ti followed by 15 nm CVD titanium nitride. This is followed by a tungsten fill to create tungsten plugs in the vias. An ALD or CVD process can be used to deposit the tungsten. Next, a copper seed layer is deposited, such as a 150 nm thick layer by PVD, followed by a copper electroplating to fill the trenches, thereby forming a grid of conducting copper bus bars. Excess copper in the field is removed, such as by CMP, down to the tungsten layer. The tungsten and barrier layers are then removed to electrically isolate the copper bus bars from the adjacent die.
Another dielectric layer is then deposited over the wafer and die, and contacts and features, such as vias and trenches, are etched over the bus bars and die, respectively. The contacts will provide electrical conductance, via a subsequently deposited seed layer, from the bus bars to the die. In different embodiments, the contacts can be a continuous straight or serpentine trench or a series of trenches or via holes. A platable barrier or a stack consisting of a barrier and a thin copper seed, is deposited, such as by PVD. During electroplating, current is conducted primarily through the bus bars to each die from the wafer edge, and then through the platable barrier or seed layer to the features within the die. Electroplating then fills the vias or other features with copper.
For each succeeding level of metallization, a large number of vias, or other pattern such as trenches, is etched down until contact can be made to the bus bar.
Utilizing the bus bars, the voltage distribution on the wafer over large scales (e.g., several die) will be approximately the same as would be seen if the cross sectional area of the bus bar was replaced by a thin sheet of the same cross sectional area. However, in contrast to the thin film case, surface scattering effects will not appreciably increase the effective resistivity. A bus bar of 60 microns wide by 3 microns deep with a 15 mm pitch is equivalent to a sheet with a resistance of 1.6 ohms/sq. If made as a thin film, this would be equivalent to 18 nm of copper (accounting for surface scattering). So bus bars on this scale would be adequate to supply plating current to the wafer.
Further, the use of the grid of bus bars eliminates the requirement that the seed layer have a low resistance per square. The sheet resistance of the seed can be increased to take advantage of this overhead. For such resistive seeds, the current will be carried by the bus bars to the die edge and then through the seed layer only from the die edge. This allows seed layers made from materials other than copper. The barrier and seed layers could potentially be combined into a single layer. Alternatively, a resistive barrier layer could be used with a copper seed layer thinner than is possible without the bus bars, allowing the barrier to be made thicker and more reliable.
This invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.